AMD, TSMC to Discuss Production of 2nm, 3nm Chips

AMD CEO Lisa Su and other senior officials are scheduled to visit Taiwan from late September to early November to discuss how to collaborate with local partners, including TSMC, chip packagers and major PC makers.

During the visit, Su will meet with TSMC CEO CC Wei to discuss cooperation, including TSMC's "N3 Plus" (likely N3P) manufacturing node and N2 (2nm) production technology. The executives will discuss forthcoming orders using either existing or future technologies.

AMD's success in recent years has been attributed to TSMC's ability to produce chips in high volumes using its highly competitive technology processes. AMD now needs to get enough factory seats and access to processor design kits (PDKs). TSMC will launch mass production on the company's N2 nodes in the second half of 2025, so AMD needs to negotiate now to incorporate the technology into 2026 products.

In addition, AMD's future success will depend on chip packaging technology, as the use of innovative packaging will only increase over time. To this end, Lisa Su will discuss the issue with local partners with TSMC, Ase Technology and SPIL. The company is currently using TSMC's 3D SoIC (system on integrated chips) platform, such as CoWoS (chip on wafer on wafer) packaging technology, and Ase's fan-out embedded bridge (FO-EB) packaging method for some of its products.